The present invention relates to techniques for achieving a higher performance of an antenna switch mounted in mobile communication devices and the like, and in particular relates to a technique effective in reducing distortion of an antenna switch used in multi band.
In addition to the voice communication and the wireless internet in the second generation mobile telephone, the advent of the third generation mobile telephone enabled a TV telephone, and a sound (music) and video distribution by the wireless internet, and thus a portable telephone system continues to grow for achieving higher functions, and the achieving of the multi-band and multi-mode is an essential requirement for portable terminals.
As the mobile telephones move to the multi-band and multi-mode, an antenna switch is having higher performance such as from SPDT (Single Pole Dual Thru) to SP4T, SP6T, and the like.
In mobile telephones, the key technical problem in the antenna switch is in that the introduction of digital modulation system such as EDGE (Enhanced Data rate for GSM Evolution) mode requires high linearity and thus a low distortion technique becomes important.
As the distortion reduction of the antenna switch in this type of mobile telephone, there is a technique in which FETs (Field Effect Transistor) constituting a SPDT switch are configured in multi-stage connection (e.g., a multi-gate configuration or a single three-stage configuration) (see Japanese Patent Application No. 2006-178928). In this case, as shown in FIG. 7B of Japanese Patent Application No. 2006-178928, the multi-stage connection allows an applied RF (Radio Frequency) voltage per stage to be dispersed, thus eliminating a pseudo-on state. Moreover, the multi stage connection allows the RF voltage applied to the FET to be dispersed, thus reducing the RF voltage per stage. Since the RF voltage applied to the gate-source capacitance (Cgs), the gate-drain capacitance (Cgd), and the on-resistance, which are the causes for generating harmonic distortion, is reduced, the harmonic distortion can be reduced.
However, the multi-stage connection by itself has a limit in further reducing the harmonic distortion, and thus a new circuit design technique is required.
As the technique for further reducing the harmonic distortion, there is a technique in which a booster circuit is provided in an antenna switch and a boost voltage generated by this booster circuit is applied to the gate electrode of the FET of a switch block, thereby increasing the gate-source voltage Vgs of a turned-off FET (see U.S. Patent laid-open No. 2004-0229577).
In the booster circuit shown in FIG. 10 of U.S. Patent laid-open No. 2004-0229577, a part of the transmission power is input to the booster circuit, and a voltage is generated in a capacitance 402 by rectification of two diodes 411, 412, and then a voltage higher than a control voltage Vc1, which is a control voltage of the FET, is output from the output terminal of the booster circuit.